In data transmission, overall power dissipation can be reduced by reducing the signal power until the signal-to-noise ratio drops too low for reliable signal detection or until the increasing receiver gain requires power to increase more rapidly than the transmitter power decreases. Since noise pick-up and offset in the receive amplifier also may be significant or dominant, the receive amplifier can be the major factor in determining both data rate capability and signal level in the transmission channel. Generally, CMOS integrated circuit technology has made it possible to decrease the power dissipation of digital circuitry, while at the same time providing high data rate capability. It is important for all CMOS data transmission circuits to have compatible performance.
In order to avoid excessive power consumption and to minimize electro-magnetic interference (EMI), it is desirable to transmit high rate data at amplitudes corresponding to power on the order of one milliwatt (approximately 300 millivolts into a 100 ohm load, for example), much lower than typical logic levels and power supply voltages. While the maximum amplitude is determined by signal power, the minimum amplitude is limited by total noise pick-up and by receiver power consumption, receiver input offset voltage, and receiver bit rate capability vs. input signal amplitude. Power consumption is important not only in its own right, but also in that it effectively limits minimum signal amplitude because there is little benefit in decreasing signal power below a certain point if doing so requires even greater increase in receiver power to compensate. Because input offset voltage will tend to affect the detected logic state just as will any other form of unwanted input signal, the input offset voltage must be included in a summation of all relevant noise. Reduced amplitude signals typically reduce speed performance, so that the receive amplifier may be the speed-limiting factor in high rate communication links. In addition, in order to realize the full advantages of differential signals, the amplifier must have low common-mode sensitivity and must operate over a relatively wide common-mode range. Thus, the receive amplifier generally plays a key role in the capabilities and limitations of high speed data communications links. Key performance criteria for a high speed data receive amplifier are:
a) high data rate capability, PA1 b) low input offset voltage, PA1 c) low power dissipation, PA1 d) low sensitivity to input amplitude variations, PA1 e) low sensitivity to common mode signals, and PA1 f) wide common-mode rejection range.
Some data receivers of the prior art have used transient positive feedback to decrease rise and fall times (i.e. with positive feedback applied only for the time required to complete a transition and then shutting off).